1. Field of the Invention
The present invention relates to a semiconductor circuit and, more specifically, to such a semiconductor circuit that includes a transistor circuit receiving an input signal having a small amplitude.
2. Description of the Related Art
In accordance with rapid development in semiconductor technology, semiconductor integrated circuits (ICs) have been operable in very high frequencies. It is, therefore, required that signal transmission among ICs and further among sets or equipments is also performed at a high speed such as a high frequency range close to 100 MHz. For this purpose, such a new signal transmission method has been proposed that signal transmission is performed with a very small amplitude from one IC (or set) to another IC (or set) instead of employing the TTL (Transistor Transistor Logic) level. Such new signal transmission methods are disclosed in, for example, "NIKKEI ELECTRONICS" 1993, 9, 27 (No. 591), pp. 269-290. One of the new methods is called "GTL" (Gunning Transceiver Logic) Transmission.
In this signal transmission, a signal to be transferred is transmitted through a transmission line with an amplitude of approximately 0.2 V to 0.5 V. Moreover, the reference voltage Vref of the signal is designed to be 0.7 to 1.2 V.
On the other hand, it is necessary for an IC itself to enlarge the amplitude of the signal thus transmitted to perform easy and/or noise-free processing on the received signal. To this end, an input buffer circuit is required to receive the signal transmitted with the GTL level and convert it into such a signal that has a relatively large amplitude.
In a conventional technique, a differential amplifier of a MOS type as shown in FIG. 1 is employed as such an input buffer. In FIG. 1, this amplifier 200 includes two P-channel MOS transistors M21 and M23, two N-channel MOS transistors M22 and M24 and one current source I21, which are connected as shown. In particular, an input signal IN having the above small amplitude is supplied to the gate of the transistor M21 and the reference voltage Vref indicative of a center level of the input signal IN is supplied to the gate of the transistor M23. The MOS differential amplifier 200 can thus convert the input signal with the GTL level into a signal with such a level that is larger than the TTL level.
However, the MOS transistor has in general a relatively low current capability. For this reason, it takes a relatively long period of time for the amplifier 200 to convert the input signal IN into a signal with a required amplitude. That is, a significant time delay occurs in the amplifier 200. If each of the MOS transistors M21 to M24 would be constituted with a large size to have large current capability, the period of time for converting the input signal IN into a signal with a large amplitude. In this case, however, power consumption is increased remarkably, and an area on a semiconductor chip occupied by the amplifier 200 is also increased.
It would be therefore considered to employ a differential amplifier of a bipolar type as an input buffer, since a bipolar transistor has higher current capability than a MOS transistor with the same size as a MOS transistor. Moreover, an NPN type bipolar transistor is preferable, since it operates at higher speed than a PNP type transistor.
However, the input signal IN has its center level (i.e., the reference level Vref) that is about 0.7 to 1.2 V as described above. For this reason, the NPN bipolar transistors receiving such a signal do not operate, cr operate in saturated conditions.